Power Safe Offline Download

ABSTRACT

The present disclosure generally relates to using a single firmware slot in a slower boot media while temporarily leveraging high speed media and dual boot designs to allow booting into a cached copy of firmware to guarantee power safety while writing the single firmware slot on the slower boot media. The device boots up with original firmware stored in a first non-volatile memory device when powered on. The device then checks a second non-volatile memory device for new firmware. If there is new firmware stored in the second non-volatile memory device, the device loads the new firmware into a volatile memory device and reboots with the new firmware. The device then writes the new firmware to the firmware slot of the first non-volatile memory device. If the device experiences a power cycle while writing the new firmware, the device can reboot with a cached copy of the new firmware.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of co-pending U.S. Non-Provisionalpatent application Ser. No. 16/057,571, filed Aug. 7, 2018, which claimsbenefit of U.S. Provisional Patent Application Ser. No. 62/561,616,filed Sep. 21, 2017, which is herein incorporated by reference.

BACKGROUND OF THE DISCLOSURE Field of the Disclosure

Embodiments of the present disclosure generally relate to a storagedevice, such as a solid state drive (SSD), and a method of operating thestorage device.

Description of the Related Art

Firmware is provided with storage devices to allow the device to performdesired functions. From time to time, firmware needs to be updated. Thisis particularly true when bugs are discovered in firmware, firmware isrewritten to perform a new task, or firmware is rewritten to performspecified tasks in a different order. Firmware updates to storagedevices can be challenging, as extreme care must be exercised in writingand correctly implementing the firmware.

Firmware updates need to be downloaded to the device, but downloadingthe firmware typically sacrifices firmware update power safety in orderto increase the speed of the download and to reduce the number of copiesof firmware in the slow boot media (i.e., NOR). As such, the slow bootmedia download is typically not power safe, and in the event of a powerloss, the device may be compromised with potentially corrupted firmware,making the device unusable.

Alternatively, the device may be power-safe, but have a long responsetime. The power-safe device may have multiple firmware slots in the slowboot media, which requires excess download time to write and update thefirmware and incurs extra costs.

Therefore, there is a need in the art to have a power-safe download thatis quick.

SUMMARY OF THE DISCLOSURE

The present disclosure generally relates to using a single firmware slotin a slower boot media while temporarily leveraging high speed media anddual boot designs to allow booting into a cached copy of firmware toguarantee power safety while writing the single firmware slot on theslower boot media. The device boots up with original firmware stored ina first non-volatile memory device when powered on. The device thenchecks a second non-volatile memory device for new firmware. If there isnew firmware stored in the second non-volatile memory device, the deviceloads the new firmware into a volatile memory device and reboots withthe new firmware. The device then writes the new firmware to thefirmware slot of the first non-volatile memory device. If the deviceexperiences a power cycle while writing the new firmware, the device canreboot with a cached copy of the new firmware.

In one embodiment, a method for operating a storage device compriseswriting new firmware to a first non-volatile memory device of thestorage device, loading the new firmware into a volatile memory deviceof the storage device from the first non-volatile memory device, andbooting the storage device with the new firmware loaded into thevolatile memory device. The method further comprises updating a firmwareslot on a second non-volatile memory device of the storage device withthe new firmware, and updating a status of the second non-volatilememory device once the firmware slot is finished updating.

In another embodiment, a method for operating a storage device havingone or more non-volatile memory devices and a volatile memory devicecomprises booting the storage device with an original firmware from afirst non-volatile memory device of the one or more non-volatile memorydevices, determining an updated firmware is available in a secondnon-volatile memory device of the one or more non-volatile memorydevices, and loading the updated firmware into the volatile memorydevice. The method further comprises rebooting the storage device withthe updated firmware loaded into the volatile memory device, writing theupdated firmware to the first non-volatile memory device, and rebootingthe storage device with the updated firmware loaded into the volatilememory device when the storage device loses power before the updatedfirmware is completely written to the first non-volatile memory device.

In yet another embodiment, a method for operating a storage devicehaving a non-volatile memory device and a volatile memory devicecomprises writing an updated firmware to a firmware slot of thenon-volatile memory device, powering on the storage device afterexperiencing a power cycle before the updated firmware could be fullywritten to the firmware slot of the non-volatile memory device, bootingthe storage device with the updated firmware loaded into the volatilememory device, re-writing the updated firmware to the firmware slot ofthe non-volatile memory device, and updating a status of thenon-volatile memory device once the firmware slot is finished writing.

In one embodiment, a data storage device comprises a plurality ofnon-volatile memory devices, one or more volatile memory devices, and acontroller coupled to the plurality of non-volatile memory devices andthe one or more volatile memory devices. The controller is configured toboot the data storage device with an original firmware from a firstnon-volatile memory device of the plurality of non-volatile memorydevices, load a firmware update to the one or more volatile memorydevices, reboot the data storage device with the firmware update loadedinto the one or more volatile memory devices, and write the firmwareupdate to the first non-volatile memory device.

In another embodiment, a data storage device comprises a plurality ofnon-volatile memory devices and one or more volatile memory devices. Thedata storage device further comprises means for booting the data storagedevice with an original firmware stored in a first non-volatile memorydevice of the plurality of non-volatile memory devices, means forwriting an updated firmware to a second non-volatile memory device ofthe plurality of non-volatile memory devices, means for storing theupdated firmware in the one or more volatile memory devices, means forrebooting the data storage device with the updated firmware stored inthe one or more volatile memory devices, and means for writing theupdated firmware to the first non-volatile memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure can be understood in detail, a more particular description ofthe disclosure, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

FIG. 1 is a schematic illustration of data storage system according toone embodiment.

FIG. 2A is a schematic illustration of a method of performing adual-boot process according to one embodiment.

FIG. 2B is a schematic illustration of a method of the storage devicehaving a single firmware slot on a NOR memory device rebooting afterexperiencing a power cycle.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements disclosed in oneembodiment may be beneficially utilized on other embodiments withoutspecific recitation.

DETAILED DESCRIPTION

In the following, reference is made to embodiments of the disclosure.However, it should be understood that the disclosure is not limited tospecific described embodiments. Instead, any combination of thefollowing features and elements, whether related to differentembodiments or not, is contemplated to implement and practice thedisclosure. Furthermore, although embodiments of the disclosure mayachieve advantages over other possible solutions and/or over the priorart, whether or not a particular advantage is achieved by a givenembodiment is not limiting of the disclosure. Thus, the followingaspects, features, embodiments and advantages are merely illustrativeand are not considered elements or limitations of the appended claimsexcept where explicitly recited in a claim(s). Likewise, reference to“the disclosure” shall not be construed as a generalization of anyinventive subject matter disclosed herein and shall not be considered tobe an element or limitation of the appended claims except whereexplicitly recited in a claim(s).

The present disclosure generally relates to using a single firmware slotin a slower boot media while temporarily leveraging high speed media anddual boot designs to allow booting into a cached copy of firmware toguarantee power safety while writing the single firmware slot on theslower boot media. The device boots up with original firmware stored ina first non-volatile memory device when powered on. The device thenchecks a second non-volatile memory device for new firmware. If there isnew firmware stored in the second non-volatile memory device, the deviceloads the new firmware into a volatile memory device and reboots withthe new firmware. The device then writes the new firmware to thefirmware slot of the first non-volatile memory device. If the deviceexperiences a power cycle while writing the new firmware, the device canreboot with a cached copy of the new firmware.

FIG. 1 is a schematic illustration of data storage system 100 accordingto one embodiment. The data storage system 100 includes a host device102 and a storage device 104. The host device 102 is coupled to thestorage device 104 both physically as well as electronically through aninterface 106 that contains one or more phys 108A-108N.

The storage device 104 includes a controller 114 that is coupled to andcommunicates with the interface 106. A power supply 120 is coupled tothe interface 106 and the controller 114. The controller 114 includesone or more processors 122A-122N. The controller 114 is coupled to oneor more fast or quick non-volatile memory devices 116A-116N, one or morevolatile memory devices 118A-118N, and one or more slow non-volatilememory devices 124A-124N. An example of a slow non-volatile memorydevice 124A-124N is a NOR memory device and an example of a fast orquick non-volatile memory device 116A-116N is a NAND memory device. Itis to be understood that NOR memory devices are but one example of theslow non-volatile memory devices 124A-124N and thus, the slownon-volatile memory devices 124A-124N are not to be limited to NORmemory devices. Additionally, it is to be understood that NAND memorydevices are but one example of the fast non-volatile memory devices116A-1164N and thus, the fast non-volatile memory devices 116A-116N arenot to be limited to NAND memory devices.

In some examples, the storage device 104 may include additionalcomponents not shown in FIG. 1 for sake of clarity. For example, thestorage device 104 may include a printed board (PB) to which componentsof the storage device 104 are mechanically attached and which includeselectrically conductive traces that electrically interconnect componentsof storage device 104, or the like. In some examples, the physicaldimensions and connector configurations of the storage device 104 mayconform to one or more standard form factors. Some example standard formfactors include, but are not limited to, 3.5″ hard disk drive (HDD),2.5″ HDD, 1.8″ HDD, peripheral component interconnect (PCI),PCI-extended (PCI-X), PCI Express (PCIe) (e.g., PCIe ×1, ×4, ×8, ×16,PCIe Mini Card, MiniPCI, etc.). In some examples, storage device 104 maybe directly coupled (e.g., directly soldered) to a motherboard of thehost device 102.

The interface 106 may operate in accordance with any suitable protocol.For example, the interface 106 may operate in accordance with one ormore of the following protocols: advanced technology attachment (ATA)(e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel, smallcomputer system interface (SCSI), serially attached SCSI (SAS),peripheral component interconnect (PCI), PCI-express, or Non-VolatileMemory Express (NVMe). The electrical connection of the interface 106(e.g., the data bus, the control bus, or both) is electrically connectedto the controller 114, providing electrical connection between the hostdevice 102 and the controller 114, allowing data to be exchanged betweenhost device the 102 and the controller 114. In some examples, theelectrical connection of the interface 106 may also permit the storagedevice 104 to receive power from the host device 102. For example, asillustrated in FIG. 1, the power supply 120 may receive power from hostdevice the 102 via the interface 106.

The storage device 104 includes the power supply 120, which may providepower to one or more components of the storage device 104 and isoptional. When operating in a standard mode, the power supply 120 mayprovide power to the one or more components using power provided by anexternal device, such as the host device 102. For instance, the powersupply 120 may provide power to the one or more components using powerreceived from the host device 102 via the interface 106. In someexamples, the power supply 120 may include one or more power storagecomponents configured to provide power to the one or more componentswhen operating in a shutdown mode, such as where power ceases to bereceived from the external device. In this way, the power supply 120 mayfunction as an onboard backup power source. Some examples of the one ormore power storage components include, but are not limited to,capacitors, super capacitors, batteries, and the like. In some examples,the amount of power that may be stored by the one or more power storagecomponents may be a function of the cost and/or the size (e.g.,area/volume) of the one or more power storage components. In otherwords, as the amount of power stored by the one or more power storagecomponents increases, the cost and/or the size of the one or more powerstorage components also increases.

The storage device 104 includes one or more volatile memory devices118A-118N, which may be used by the controller 114 to temporarily storeinformation. In some examples, the controller 114 may use the one ormore volatile memory devices 118A-118N as a cache. For instance, thecontroller 114 may store cached information in the one or more volatilememory devices 118A-118N until the cached information is written to theone or more non-volatile memory devices 116A-116N or 124A-124N. The oneor more volatile memory devices 118A-118N may consume power receivedfrom the power supply 120 to maintain the data stored in the one or morevolatile memory devices 118A-118N. Examples of volatile memory include,but are not limited to, random-access memory (RAM), dynamic randomaccess memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM(SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, and the like)). Inat least one implementation, the one or more volatile memory devices118A-118N comprise at least one DRAM device.

The storage device 104 includes the controller 114, which may manage oneor more operations of the storage device 104. For instance, thecontroller 114 may manage the reading of data from and/or the writing ofdata to the one or more non-volatile memory devices 116A-116N, 124A-124Nand the one or more volatile memory devices 118A-118N. In some examples,the controller 114 may manage the reading of data from and/or thewriting of data to the one or more non-volatile memory devices 116A-116Nor one or more volatile memory devices 118A-118N by exchanging signalswith the one or more non-volatile memory devices 116A-116N or the one ormore volatile memory devices 118A-118N. As discussed above, thecontroller 114 may exchange signals with the one or more non-volatilememory devices 116A-116N or the one or more volatile memory devices118A-118N in accordance with a communication protocol.

The controller 114 includes one or more processors 122A-122N. Theprocessors 122A-122N may be configured to execute tasks. The tasks maybe of different types, and, in some examples, each respective type oftask may be stored in or associated with a respective task queue whilewaiting for execution by the processor 122A-122N. The different types oftasks may include, for example, front end tasks, which may includereceiving and interpreting instructions received from the host device102. Other types of tasks including caching; back-end tasks, which mayinclude reading data from or writing data to non-volatile memory 116;housing-keeping, which may include garbage collection, wear leveling,TRIM, or the like; and system tasks. In some examples, the processor122A-122N may be referred to as a computer unit, a processing unit, acore, or a central processing unit (CPU).

As will be discussed in greater detail below, a dual-boot process can beused when new firmware is to be installed. Specifically, the existingfirmware remains intact and the new firmware is downloaded to a newnon-volatile location on a faster non-volatile memory (for example, theone or more non-volatile memory devices 116A-116N). The existingfirmware will typically be stored on the slower non-volatile memory (forexample, the one or more non-volatile memory devices 124A-124N).

As discussed herein, a single firmware slot in a NOR memory device isused. High speed media is leveraged in the dual boot process so thattemporarily booting from a cached copy of firmware is used to guaranteepower safety while writing the single firmware slot on the slower bootmedia. In a basic sense, the bootloader is kept separate from theupdated firmware and is not updateable in a power safe way, but iscapable of bringing up the high speed media.

In a specific example, the new firmware is written to non-volatilememory on a fast non-volatile memory device such as a NAND memory device116A, rather than a slow non-volatile memory like a NOR memory device124A. Typically, a NOR memory device 124A is used for firmware storagebecause the NOR memory device 124A is available immediately on power-up.The boot is initially run through the NOR memory device 124A, and then abootloader (e.g., a portion of the firmware) brings up the NAND memorydevice 116A to check whether the NAND memory device 116A has a downloadpackage for the NOR memory device 124A. The download package includesnew firmware, but does not include a new or updated bootloader. Thus,the original bootloader is capable of bringing up the NAND memory device116A, and is separate and immutable from the new firmware. The newfirmware that is in the NAND memory device 116A is loaded into a DRAMdevice 118A and booted into via the DRAM device 118A.

After booting with the new firmware through the DRAM device 118A, thefirmware in the NAND memory device 116A is written to the NOR memorydevice 124A. Since the NOR memory device 124A includes only a singlefirmware slot, the bootloader is kept separate from the firmware so thatthe bootloader cannot be corrupted by a power cycle. The writing to thesingle firmware slot of the NOR memory device 124A, or syncing, occursin block fashion. Only once the syncing is complete is a status of“done” sent to the one or more processors 122A-122N indicating thesyncing is complete. Even if a power cycle occurs while the new firmwareis being written to the NOR memory device 124A, the new firmware willstill be used so long as the new firmware has been written into the NANDmemory device 116A and loaded into the DRAM device 118A. Thus, thefirmware download is power-safe as well as fast.

Once the storage device 104 receives the new firmware from the hostdevice 102, the firmware will be written to the reserved area (i.e.,NAND 116A), loaded into memory (i.e., DRAM 118A), booted into the DRAMdevice 118A, and then updated to the single firmware slot on the NORmemory device 124A. The copy of the firmware on the NAND memory device116A is uploaded by the bootloader and then booted into if a power cycleoccurs before the NOR firmware slot is fully updated. The NOR firmwareslot is written completely before the status is returned on the finalwrite buffer of the download. In other words, the status is not returneduntil the writing to the NOR memory device 124A is complete.

The advantages of the disclosure include the NOR memory device 124Ausage being minimal, power safety is maintained, slow download times arereduced, and device cost is reduced. The firmware download time isreduced and optimized by utilizing a single firmware slot on the NORmemory device 124A. Additionally, by first writing the new firmware tothe NAND memory device 116A and loading the new firmware into the DRAMdevice 118A, the firmware download is power-safe. If a power cycleoccurs while the new firmware is being written to the firmware slot onthe NOR memory device 124A, the storage device 104 can reboot with thenew firmware loaded into the DRAM device 118A, and re-write the newfirmware to the NOR firmware slot. Therefore, the storage device 104 ispower-safe with quick download times.

FIG. 2A is a schematic illustration of a method 200 of a storage deviceperforming a dual-boot process according to one embodiment. The method200 may be executed by the data storage system 100 having the hostdevice 102 and the storage device 104. The method 200 begins at item 202where a storage device begins to power on.

In item 204, a controller, such as controller 114 of FIG. 1, reads theexisting firmware which resides in the slow non-volatile memory, such asa NOR memory device. The NOR memory device may be a NOR memory devicefrom the one or more NOR memory devices 124A-124N of FIG. 1. The storagedevice begins to boot up with the existing or original firmware storedon the NOR memory device in item 206. In item 208, as the storage deviceis booting up, the controller checks a NAND memory device to determineif there is new firmware. The NAND memory device may be a NAND memorydevice from the one or more NAND memory devices 116A-116N of FIG. 1. Thecontroller may use a bootloader stored in a NOR memory device to bringup and check the NAND memory device for new firmware. The NAND memorydevice may receive new firmware as a download package from the hostdevice, and may store the new firmware download package to a reservedarea of the NAND memory device. The new firmware download package doesnot include a new bootloader. As such, the bootloader is not updatablein a power safe way.

If there is no new firmware written in the NAND memory device in item208, then the boot up continues through the NOR memory device in item210. If, however, there is new firmware in the NAND memory device, thenthe method 200 proceeds to item 212. In item 212, the new firmware thatis in the NAND memory device is cached or loaded into a DRAM devicewhile the boot up through the NOR memory device continues. The DRAMdevice may be a DRAM device from the one or more volatile memory devices118A-118N of FIG. 1. The new firmware may be loaded into the DRAM deviceusing the bootloader.

In item 214, once the new firmware is loaded into the DRAM device, thestorage device is rebooted through the new firmware. In item 216, oncethe reboot with the new firmware is complete, the single firmware sloton the NOR memory device is updated with the new firmware. The newfirmware is written to the firmware slot of the NOR memory device sothat subsequent boot-ups will occur through the NOR memory device. Byutilizing the dual boot design to reboot the storage device through thecached copy of the updated firmware via the DRAM device, the updatedfirmware can be written to the NOR memory device and firmware updatepower safety is not sacrificed.

In item 218, a determination is made as to whether the write to the NORmemory device was completed. If the determination is made that the writeto the NOR memory device has been completed in item 218, then the statusof the NOR memory device is updated in item 220. Updating the status ofthe NOR memory device indicates that the new firmware was successfullyand completely written to the NOR memory device, and allows the storagesystem to boot up with the new firmware stored on the NOR memory devicefor subsequent power ups of the storage device.

If the firmware stored in the NOR memory device has not been updated(i.e., the new firmware update has not been completely written to thesingle firmware slot of the NOR memory device), then the status of theNOR memory device remains unchanged in item 222. A power cycle or powerloss may interrupt the write of the new firmware to the firmware slot ofNOR memory device and cause the firmware stored in the NOR memory deviceto not be updated. Thus, the status of the NOR memory device remainingunchanged in item 222 may indicate that the NOR memory device containscorrupted or non-operational firmware. Following item 222 of the method200, storage device may proceed to method 250 of FIG. 2B.

FIG. 2B is a schematic illustration of a method 250 of the storagedevice having a single firmware slot on a NOR memory device rebootingafter experiencing a power cycle. The method 250 may directly follow themethod 200. For example, if the storage device experiences a power cycleor power loss in item 216 of the method 200, the storage device mayproceed to execute the method 250.

The method 250 begins at item 252, where the storage device experiencesa power cycle while writing or syncing the new/updated firmware to thesingle firmware slot of the NOR memory device. If there is a power lossor power cycle while writing or syncing the updated firmware to the NORdevice, the updated firmware may not be completely written to the NORmemory device, and as such, may be corrupt. The storage device is unableto properly boot up with corrupt firmware.

In item 254, the storage device powers on, and a processor, such as aprocessor 122A-122N of FIG. 1, loads the bootloader. The bootloader isstored in the NOR memory device, and thus, the bootloader is availableimmediately on power-up. The updated firmware does not include an updateto the bootloader. The bootloader is kept separate and immutable duringthe firmware update of the NOR memory device in item 216 of method 200.As such, the bootloader will not be corrupted by a power cycle.

In item 256, the bootloader determines whether the firmware stored inthe NOR memory device is corrupt or non-operational. If the NOR memorydevice contains operational firmware, the method 250 proceeds to item258. In item 258, the storage device is booted up with the operationalfirmware stored in the NOR memory device. If the firmware stored in theNOR is corrupted or non-operational, the method 250 proceeds to item260.

In item 260, the bootloader brings up the NAND memory device and findsthe updated firmware package. The updated firmware package may bewritten to a reserved area of the NAND memory device. After thebootloader finds the updated firmware package stored in the NAND memorydevice, the method 250 proceeds to item 262. In item 262, the bootloaderloads the updated firmware package into the DRAM device and the storagedevice reboots into the updated firmware via the DRAM device.

After the storage device is rebooted with the updated firmware, thestorage device continues to sync or rewrite the updated firmware to theNOR memory device to fix the corruption in item 264. If the updatedfirmware is fully written or synced to the NOR memory device in item264, the status of the NOR memory device may updated, such as in item220 of the method 200.

Utilizing a bootloader that is separate and immutable during thefirmware update to the NOR memory device and storing a copy of theupdated firmware on the NAND memory device allows the storage device toupdate firmware in a power-safe manner. If the write of the updatedfirmware to the firmware slot of the NOR memory device is interrupted orincomplete, the bootloader can bring up the NAND memory device and loadthe updated firmware into the DRAM device. Thus, the storage device canreboot into the updated firmware via the DRAM device, rather thanthrough corrupt or non-operational firmware stored the NOR memorydevice.

Even if the storage device experiences a power cycle while writing thenew/updated firmware to the NOR firmware slot, a copy of the updatedfirmware is still stored uncorrupted in the NAND memory device. Thus,the storage device can use the non-updated bootloader to bring up a copyof the updated firmware stored in the NAND memory device and load theupdated firmware into the DRAM device to reboot into. As such, thefirmware update process is power-safe, and the storage device will notbe rendered unusable. Furthermore, syncing the NOR memory device withthe updated firmware can be accomplished quickly, as the NOR memorydevice utilizes only a single firmware slot, and there is no need toexpend excess time to update multiple firmware slots.

By using a dual-boot process and a single firmware slot on the NORmemory device, new or updated firmware stored in the NAND memory device(or other fast non-volatile memory) can be booted into via the DRAMdevice and safely written to the NOR memory device (or other slownon-volatile memory) in a power-safe manner without sacrificing speed.Thus, the NOR memory device usage is minimal, power safety ismaintained, slow download times are reduced, and device cost is reduced.

The techniques described in this disclosure may be implemented, at leastin part, in hardware, software, firmware, or any combination thereof.For example, various aspects of the described techniques may beimplemented within one or more processors, including one or moremicroprocessors, digital signal processors (DSPs), application specificintegrated circuits (ASICs), field programmable gate arrays (FPGAs), orany other equivalent integrated or discrete logic circuitry, as well asany combinations of such components. The term “processor” or “processingcircuitry” may generally refer to any of the foregoing logic circuitry,alone or in combination with other logic circuitry, or any otherequivalent circuitry. A control unit including hardware may also performone or more of the techniques of this disclosure.

Such hardware, software, and firmware may be implemented within the samedevice or within separate devices to support the various techniquesdescribed in this disclosure. In addition, any of the described units,modules or components may be implemented together or separately asdiscrete but interoperable logic devices. Depiction of differentfeatures as modules or units is intended to highlight differentfunctional aspects and does not necessarily imply that such modules orunits must be realized by separate hardware, firmware, or softwarecomponents. Rather, functionality associated with one or more modules orunits may be performed by separate hardware, firmware, or softwarecomponents, or integrated within common or separate hardware, firmware,or software components.

The techniques described in this disclosure may also be embodied orencoded in an article of manufacture including a computer-readablestorage medium encoded with instructions. Instructions embedded orencoded in an article of manufacture including a computer-readablestorage medium encoded, may cause one or more programmable processors,or other processors, to implement one or more of the techniquesdescribed herein, such as when instructions included or encoded in thecomputer-readable storage medium are executed by the one or moreprocessors. Computer readable storage media may include random accessmemory (RAM), read only memory (ROM), programmable read only memory(PROM), erasable programmable read only memory (EPROM), electronicallyerasable programmable read only memory (EEPROM), flash memory, a harddisk, a compact disc ROM (CD-ROM), a floppy disk, a cassette, magneticmedia, optical media, or other computer readable media. In someexamples, an article of manufacture may include one or morecomputer-readable storage media.

In some examples, a computer-readable storage medium may include anon-transitory medium. The term “non-transitory” may indicate that thestorage medium is not embodied in a carrier wave or a propagated signal.In certain examples, a non-transitory storage medium may store data thatcan, over time, change (e.g., in RAM or cache).

In one embodiment, a method for operating a storage device compriseswriting new firmware to a first non-volatile memory device of thestorage device, loading the new firmware into a volatile memory deviceof the storage device from the first non-volatile memory device, andbooting the storage device with the new firmware loaded into thevolatile memory device. The method further comprises updating a firmwareslot on a second non-volatile memory device of the storage device withthe new firmware, and updating a status of the second non-volatilememory device once the firmware slot is finished updating.

The first non-volatile memory device may be a NAND memory device. Thesecond non-volatile memory device may be a NOR memory device. Thevolatile memory device may be a DRAM device. The method may furthercomprise rebooting the storage device with the new firmware loaded intothe volatile memory device before updating the status of the secondnon-volatile memory device when the storage device power cycles whileupdating the firmware slot on the second non-volatile memory device withthe new firmware.

In another embodiment, a method for operating a storage device havingone or more non-volatile memory devices and a volatile memory devicecomprises booting the storage device with an original firmware from afirst non-volatile memory device of the one or more non-volatile memorydevices, determining an updated firmware is available in a secondnon-volatile memory device of the one or more non-volatile memorydevices, and loading the updated firmware into the volatile memorydevice. The method further comprises rebooting the storage device withthe updated firmware loaded into the volatile memory device, writing theupdated firmware to the first non-volatile memory device, and rebootingthe storage device with the updated firmware loaded into the volatilememory device when the storage device loses power before the updatedfirmware is completely written to the first non-volatile memory device.

The first non-volatile memory device may be a NOR memory device. The NORmemory device may comprise a single firmware slot. The secondnon-volatile memory device may be a NAND memory device. The method mayfurther comprise performing a power on procedure for the storage deviceprior to the booting the storage device with the original firmware fromthe first non-volatile memory device. The performing the power onprocedure for the storage device prior to the booting the storage devicewith the original firmware from the first non-volatile memory device maybe performed by a controller.

In yet another embodiment, a method for operating a storage devicehaving a non-volatile memory device and a volatile memory devicecomprises writing an updated firmware to a firmware slot of thenon-volatile memory device, powering on the storage device afterexperiencing a power cycle before the updated firmware could be fullywritten to the firmware slot of the non-volatile memory device, bootingthe storage device with the updated firmware loaded into the volatilememory device, re-writing the updated firmware to the firmware slot ofthe non-volatile memory device, and updating a status of thenon-volatile memory device once the firmware slot is finished writing.

The volatile memory device is a DRAM device. The non-volatile memorydevice may be a NOR memory device. The method may further comprisechecking a NAND memory device of the storage device for new firmwareprior to the writing the updated firmware to the firmware slot of theNOR memory device. The method may further comprise storing the updatedfirmware in the volatile memory device before writing the updatedfirmware to the firmware slot of the NOR memory device.

In one embodiment, a data storage device comprises a plurality ofnon-volatile memory devices, one or more volatile memory devices, and acontroller coupled to the plurality of non-volatile memory devices andthe one or more volatile memory devices. The controller is configured toboot the data storage device with an original firmware from a firstnon-volatile memory device of the plurality of non-volatile memorydevices, load a firmware update into the one or more volatile memorydevices, reboot the data storage device with the firmware update loadedinto the one or more volatile memory devices, and write the firmwareupdate to the first non-volatile memory device.

The plurality of non-volatile memory devices may comprise one or moreNOR memory devices and one or more NAND memory devices. The controllermay be further configured to write the firmware update to a secondnon-volatile memory device of the plurality of non-volatile memorydevices. The first non-volatile memory device may be a NOR memorydevice, and the second non-volatile memory device may be a NAND memorydevice. The controller may be further configured to reboot the datastorage device with the firmware update loaded into the one or morevolatile memory devices when the data storage device power cycles whilewriting the firmware update to the first non-volatile memory device.

In another embodiment, a data storage device comprises a plurality ofnon-volatile memory devices and one or more volatile memory devices. Thedata storage device further comprises means for booting the data storagedevice with an original firmware stored in a first non-volatile memorydevice of the plurality of non-volatile memory devices, means forwriting an updated firmware to a second non-volatile memory device ofthe plurality of non-volatile memory devices, means for storing theupdated firmware in the one or more volatile memory devices, means forrebooting the data storage device with the updated firmware stored inthe one or more volatile memory devices, and means for writing theupdated firmware to the first non-volatile memory device.

The data storage device may further comprise means for updating a statusof the first non-volatile memory device, wherein the status of the firstnon-volatile memory device indicates whether the updated firmware wasentirely written to the first non-volatile memory device. The one ormore volatile memory devices may comprise at least one DRAM device. Theupdated firmware may be stored in the at least one DRAM device of theone or more volatile memory devices. The data storage device may furthercomprise means for rebooting the data storage device with the updatedfirmware after the data storage device power cycles while writing theupdated firmware to the first non-volatile memory device. The firstnon-volatile memory device may be a NOR memory device and the secondnon-volatile memory device may be a NAND memory device.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

What is claimed is:
 1. A method for operating a storage device havingone or more non-volatile memory devices and a volatile memory device,comprising: booting the storage device with an original firmware from afirst non-volatile memory device of the one or more non-volatile memorydevices; determining an updated firmware is available in a secondnon-volatile memory device of the one or more non-volatile memorydevices; loading the updated firmware into the volatile memory device;rebooting the storage device with the updated firmware loaded into thevolatile memory device; writing the updated firmware to the firstnon-volatile memory device; and rebooting the storage device with theupdated firmware loaded into the volatile memory device when the storagedevice loses power before the updated firmware is completely written tothe first non-volatile memory device.
 2. The method of claim 1, whereinthe first non-volatile memory device is a NOR memory device.
 3. Themethod of claim 2, wherein the NOR memory device comprises a singlefirmware slot.
 4. The method of claim 1, wherein the second non-volatilememory device is a NAND memory device.
 5. The method of claim 1, furthercomprising performing a power on procedure for the storage device priorto the booting the storage device with the original firmware from thefirst non-volatile memory device.
 6. The method of claim 5, wherein theperforming the power on procedure for the storage device prior to thebooting the storage device with the original firmware from the firstnon-volatile memory device is performed by a controller.
 7. A method foroperating a storage device having a non-volatile memory device and avolatile memory device, comprising: writing an updated firmware to afirmware slot of the non-volatile memory device; powering on the storagedevice after experiencing a power cycle before the updated firmwarecould be fully written to the firmware slot of the non-volatile memorydevice; booting the storage device with the updated firmware loaded intothe volatile memory device; re-writing the updated firmware to thefirmware slot of the non-volatile memory device; and updating a statusof the non-volatile memory device once the firmware slot is finishedwriting.
 8. The method of claim 7, wherein the volatile memory device isa DRAM device.
 9. The method of claim 7, wherein the non-volatile memorydevice is a NOR memory device.
 10. The method of claim 9, furthercomprising checking a NAND memory device of the storage device for newfirmware prior to the writing the updated firmware to the firmware slotof the non-volatile memory device.
 11. The method of claim 9, furthercomprising storing the updated firmware in the volatile memory devicebefore writing the updated firmware to the firmware slot of thenon-volatile memory device.
 12. A data storage device, comprising: anon-volatile memory device; a volatile memory device; and a controllercoupled to the non-volatile memory device and the volatile memorydevice, wherein the controller is configured to: boot the data storagedevice from the non-volatile memory device; determine an updatedfirmware is available; load the updated firmware into the volatilememory device; reboot the storage device with the updated firmware;write the updated firmware to the non-volatile memory device; and rebootthe storage device with the updated firmware after experiencing a powercycle before the updated firmware could be fully written to thenon-volatile memory device.
 13. The data storage device of claim 12,wherein the rebooting with the updated firmware is from the volatilememory when the storage device experiences the power cycle.
 14. The datastorage device of claim 12, wherein the non-volatile memory devicecomprises one or more NOR memory devices and one or more NAND memorydevices.
 15. The data storage device of claim 12, wherein the controlleris further configured to update a status of the non-volatile memorydevice, wherein the status of the non-volatile memory device indicateswhether the updated firmware was entirely written to the non-volatilememory device.
 16. The data storage device of claim 12, wherein thevolatile memory device comprises at least one DRAM device.
 17. The datastorage device of claim 16, wherein the updated firmware is stored inthe at least one DRAM device of the volatile memory device.
 18. The datastorage device of claim 12, wherein the controller is further configuredto reboot the data storage device with the updated firmware after thedata storage device power cycles while writing the updated firmware tothe non-volatile memory device.
 19. The data storage device of claim 12,wherein the controller is configured to boot the data storage devicefrom the non-volatile memory device while determining an updatedfirmware is available.
 20. The data storage device of claim 12, whereinbooting the data storage device comprises booting from NOR and whereinloading the updated firmware comprises loading the updated firmware tothe volatile memory from NAND.